1. Field of the Invention
The present invention relates to a high speed stack circuit for a register in a one chip microcomputer.
2. Description of the Related Arts
A microcomputer mounting a CPU (central processing apparatus), ROM (read only memory), RAM (random access memory), etc., on one chip transfers data in each portion by using common bus lines. When an operation is carried out by absorbing the data from the RAM to internal registers of the CPU, the process is carried out by issuing an instruction previously stored in the ROM.
Such program can be latched as a routine formed usually by many instructions. In such a process, when a main routine is carried out with a constant order, if an IRQ (interrupt request) is caused by an external source when the routine reaches a certain step, the process of the main routine must be discontinued at that step and the IRQ routine processed with priority. In this case, since the IRQ routine also utilizes many registers, the following stack process is required. That is, the content of the registers, in the state wherein execution of a certain main routine is saved to a region of the RAM instructed by a stack pointer, and subsequently, upon completion of the processing of the IRQ routine, processing of the main routine is resumed from an instruction following the certain instruction, and thus the saved content is restored in the previously used registers.
If, as in the conventional stack system, an internal BUS is used, one cycle is required per one register transfer (it is assumed that the number of bits of the register is the same as the number of lines of the bus). This leads to a disadvantage in that larger the number of registers, the more time is required for the stack. A similar situation occurs when it is returned from the IRQ routine by a return interrupt instruction (RTI).
To improve this situation, a system has been proposed in which registers exclusively used for the stack are provided internally in the CPU. According to this system, since a data stack for the RAM is not necessary, a high speed can be realized (stacked can be accomplished by one cycle). However, the registers exclusively used for the stack are exclusive hardware, and thus can not be used for storing and reading arbitrary data such as in a RAM, and accordingly can not be used for another purpose. Especially, nesting is restricted by the capacity of the stack exclusive registers, and consequently for a multistage nesting, multi-stage stack exclusive registers must be provided. This means that a large register capacity is required, but further, since these registers are not always used, much of the capacity is wasted.